In conventional photolithographic processing, circuit elements to be created in an integrated circuit are formed by exposing a semiconductor wafer through a photolithographic mask or reticle having a pattern of features formed thereon. The wafer is then chemically and mechanically processed to create the corresponding circuit elements on the wafer.
As the size of the features on the mask or reticle become smaller than the wavelength of light used to expose the mask or reticle, optical and other process distortions can occur such that the shape of the circuit elements created on the wafer may vary substantially from the desired pattern of features. Therefore, most photolithographic processing uses one or more resolution enhancement techniques, such as optical and process correction (OPC), adding sub resolution assist features (SRAFs), etc., to minimize the distortions.
Another technique used to increase the fidelity with which a pattern of circuit elements is created on a wafer is to use different illumination methods. For example, double exposure techniques create a pattern of circuit elements by exposing masks with one illumination pattern that is optimized to print features that are oriented in a particular direction onto the wafer. Another illumination pattern then prints another set of features that are oriented in a different direction in order to create the desired pattern of circuit elements on the wafer. One form of double exposure that is becoming more popular in photolithographic processing is double dipole exposure. With double dipole exposure, a first exposure is performed with a dipole illumination pattern oriented in a first (e.g., X) direction and a second exposure is made with a dipole illumination pattern oriented in a direction perpendicular (i.e., Y) direction to that of the first illumination pattern.
With dipole illumination, features, or portions thereof, of a desired layout print with a better image fidelity when they are oriented perpendicular to the orientation of the dipole illumination pattern. That is, design features that are oriented in a vertical direction are best imaged when exposed with a dipole illumination pattern that is oriented horizontally. Similarly, horizontally oriented features, or portions thereof, are best imaged when exposed with a dipole illumination pattern that is oriented in the vertical direction.
Because most design layouts include features, and portions thereof, that are oriented in both the horizontal and vertical directions, attempts have been made to develop software tools for the production of masks that allow the exposure of features that are better oriented for a particular dipole illumination pattern and prevent the exposure of features that are not optimally oriented. One technique for doing this is to place large shields over the features that are not optimally oriented for the illumination pattern in question. While such a technique can work in theory, it is difficult to develop software algorithms for converting layout data into mask data including shields on a mask. Therefore, there is a need for a system which can automatically analyze a desired layout pattern and prepare mask data for use with multiple exposure fabrication techniques.